1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a data latching type dynamic random access memory (DRAM) which has a data latching circuit provided at a stage succeeding to a sense amplifier for sensing readout data from a memory cell and which transfers data between the data latching circuit and a data bus at high speed.
2. Description of the Related Art
As the integrated circuit technology is increasingly developed, semiconductor memory devices, especially DRAMs are widely used in the electronics field. Since the memory capacity of the DRAM can be made larger, the application thereof to memories such as an image memory which requires a large memory capacity is developed, but in this application field, it is necessary to read out stored data successively and at high speed. When reading out memory data, the most important factor for determining the readout time is time for readout of data from a memory cell to a sense amplifier. Therefore, various attempts are made to apparently eliminate the readout time. For example, a DRAM with data latch is provided in which a latch circuit is connected between the sense amplifier and the I/O buffer and a readout data is temporarily held in the latch circuit.
FIG. 1 shows part of the general construction of the DRAM with data latch. The DRAM with data latch has a construction in which a data latch circuit is provided at a stage next to the sense amplifier in the memory core portion of a standard DRAM. That is, in FIG. 1, 11 denotes an address buffer, 12 a row decoder, 13 a DRAM cell array, 14 sense amplifiers, 15 transfer gates, 16 data latch circuits, 17 a column decoder, 18 column selection gates, 19 a data bus, 20 an input/output buffer, 21 a control signal buffer, and 22 an internal control signal generator.
If the DRAM cell array 13 has a construction of m rows.times.n columns, n data latch circuits 16, that is, data latch circuits of a number capable of holding data of one row are arranged. This construction is similar to that in which the cache portion of a Cache DRAM is constructed by a data latch circuit of m rows.times.n columns.
Next, the operation of the DRAM with data latch is explained. In the readout operation, when an address signal is input and a word line (not shown) selected by the row decoder 12 is activated, n data items (data items on the same row) are read out from DRAM cells (not shown) corresponding to the selected word line to the sense amplifiers 14 and respectively latched therein. Further, the transfer gates 15 between the sense amplifiers 14 and the data latch circuits 16 are turned on by a control signal generated from the internal control signal generator 22 and data items latched by the sense amplifiers 14 are transferred to the respective data latch circuits 16. Then, latch data in the data latch circuit 16 is output to an external data bus via one of the column selection gates 18 selected by the column decoder 17, data bus 19 and input/output buffer 20.
In the above operation, the transfer gates 15 are turned off when data is transferred to the data latch circuit 16 so as to permit the DRAM cell array 13 and sense amplifiers 14 to be operated independently from the data latch circuits 16 and the succeeding stage circuits. Based on this fact, a next row address signal is input while data on the same row is transferred between the data latch circuit 16 and the data bus 19. If new data items on the same row corresponding to the new row address are read out from the DRAM cell array 13 to the sense amplifiers 14, it becomes possible to transfer the new data items from the sense amplifiers 14 to the data latch circuits 16 by turning on the transfer gates 15 again when transfer of latch data from the data latch circuit 16 to the external data bus is completed.
As a result, when viewing the DRAM from the external data bus side, the time (which is normally 50 ns or more) necessary for reading out data corresponding to the row address input from the DRAM cell array 13 to the sense amplifiers 14 is apparently eliminated. That is, it has an advantage that new data can be read out from the data latch circuit 16 again when a short period of time (which is normally 10 ns or less) necessary for turning off the transfer gates 15 has elapsed after the transfer gates 15 are turned on to transfer previous data items from the sense amplifiers 15 to the data latch circuits 16.
FIG. 2 shows the conventional construction corresponding to one column of the DRAM cell array in FIG. 1 and including a bit line pair (BL, /BL), sense amplifier 14, transfer gate 15, data input/output lines (DL, /DL), data latch circuit 16 and column selection gate 18. In FIG. 2, N1 and N2 denote NMOS transistors of the transfer gate, XFER denotes a control signal for the transfer gate, N5 and N6 denote NMOS transistors of the column selection gate, and CSL denotes a control signal for the column selection gate.
Conventionally, as the data latch circuit 16, a static latch circuit as shown in the drawing is used. The static latch circuit includes a P type latch circuit constructed by PMOS transistors P3, P4 and an N type latch circuit constructed by NMOS transistors N3, N4. DBP denotes an activation signal for the P type latch circuit, /DBN denotes an activation signal for the N type latch circuit, and the states of DL, /DL are latched when the former is changed from "L" to "H" and the latter changes from "H" to "L".
The static latch circuit 16 has an advantage that the refreshing operation for the latching operation is not necessary since latched data is not lost with an elapse of time, but since the PMOS transistors P3, P4 and NMOS transistors N3, N4 are used, an isolation region for electrically isolating an N well for forming a PMOS transistor from a P well for forming an NMOS transistor becomes necessary, thereby significantly increasing the chip size of the DRAM.
As described above, in the conventional DRAM with data latch, the static latch circuit is used and the isolation region for isolation between the N well for forming the PMOS transistor and the P well for forming the NMOS transistor is necessary, thereby causing a problem that the chip size of the DRAM is significantly increased.